Integration of high-k gate stack systems into planar CMOS process flows

Abstract

We review several gate stack fabrication issues critical for robust, commercially viable tools, including assessment of possible fab contamination due to the higher-k gate dielectrics and the role of subsequent thermal procedures during, for example, source/drain anneals (including the importance of the oxygen partial pressure) to ensure their compatibility with conventional planar polysilicon CMOS transistor fabrication processes.