H. Shimano

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture

N. Sakashita, Y. Nitta, K. Shimomura et al. · IEEE Journal of Solid-State Circuits · 1996 · 23 citations

Electrical Engineering, Engineering, Vlsi Design +11

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique

K. Shimomura, H. Shimano, N. Sakashita et al. · IEEE Journal of Solid-State Circuits · 1997 · 21 citations

Low-power Electronics, Electrical Engineering, Engineering +11

Approaches to extra low voltage DRAM operation by SOI-DRAM

T. Eimori, T. Oashi, Fukashi Morishita et al. · IEEE Transactions on Electron Devices · 1998 · 20 citations

Hardware Security, Low-power Electronics, Electrical Engineering +10

16 Mb DRAM/SOI technologies for sub-1 V operation

T. Oashi, T. Eimori, Fukashi Morishita et al. · 2002 · 18 citations

Low-power Electronics, Dual Gate Cmos, Electrical Engineering +11

A built-in self-test circuit with timing margin test function in a 1 Gbit synchronous DRAM

N. Sakashita, F. Okuda, K. Shimomura et al. · 2002 · 15 citations

Gbit Synchronous Dram, Engineering, Vlsi Design +18