IEEE Journal of Solid-State Circuits · 1996 · 23 citations · 13 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureMemorySystem-on-chip DesignDistributed Memory SystemsMemory DevicesMemory HierarchyMemory Hierarchy DesignMemory Subsystem DesignUnified Memory SystemsHierarchical Memory ArchitectureHigh-speed OperationMain Memory OrganizationMemory Built-in Self-testMemory CapacityMicroprocessor Built-in Self-testThree-dimensional MemoryUnified Memory
This paper describes key techniques for a 1.6-GB/s high data-rate 1-Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are targeted to the advanced unified memory system in which a single DRAM (array) is used as both the main memory and the three-dimensional (3-D) graphics frame memory in a time sharing fashion. The 200-MHz high-speed operation is achieved by the unique hierarchical square-shaped memory block (SSMB) layout and the novel distributed bank (D-BANK) architecture. A 0.29 /spl mu/m/sup 2/ cell and 581.8 mm/sup 2/ small die area are achieved using 0.15-/spl mu/m CMOS technology. The /spl times/61 chip uses 196-pin BGA type chip-scale-package (CSP). Implementation of a built-in self-test (BIST) circuit with a margin test capability is also described.
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A 64Kb full CMOS RAM with divided word line structure
Masahiko Yoshimoto, Keiko Anami, Hirofumi Shinohara et al. · 1983 · 46 citations
Engineering, Computer Engineering, Electrical Engineering +14
An experimental 220 MHz 1 Gb DRAM
Masashi Horiguchi, T. Sakata, Tomonori Sekiguchi et al. · 2002 · 29 citations