Kazutami Arimoto - Concepedia

Author

Kazutami Arimoto

Mitsubishi Electric (Japan)ORCID

Also Known As

K. ARIMOTO, K. Arimoto, KAZUTAMI ARIMOTO, Kanna Arimoto, Kazutami ARIMOTO, Kazutami Arimoto, Y. Matsuoka

244

Publications

1.3K

Citations

H-Index

Concepts

All Affiliations

Mitsubishi Electric (Japan)Renesas Electronics (Japan)Mitsubishi Group (Japan)Renesas Electronics (United States)Hiroshima University

About

Kazutami Arimoto is an author at Mitsubishi Electric (Japan) specializing in computer engineering, engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	19	39	894
2	Computer Engineering	19	39	894
3	Electrical Engineering	16	26	578
4	Computer Science	12	17	474
5	Applied Physics	1	1	41

Kazutami Arimoto

Publications

904

Citations

H-Index

Page 1

	Year	Citations
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture Haruhiko Noda, Kazunari Inoue, M. Kuroiwa, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignSmall Cell SizeDtcam CellPipelined Hierarchical Searching	2005	104
A built-in Hamming code ECC circuit for DRAMs K. Furutani, Kazutami Arimoto, Hiroshi Miyamoto, IEEE Journal of Solid-State Circuits Hardware SecurityError CheckingEngineeringError Control TechniqueSynchronous Design	1989	69
A 40GOPS 250mW massively parallel processor based on matrix architecture M. Nakajima, Haruhiko Noda, K. Dosaka, EngineeringMatrix Processing EngineComputer ArchitectureSupercomputer ArchitectureProcessor Architecture	2006	52
An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology K. Suma, T. Tsuruda, Hideto Hidaka, IEEE Journal of Solid-State Circuits Low-power ElectronicsElectrical EngineeringCmos/simox TechnologyData Retention TimeVlsi Design	1994	41
Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs T. Yamagata, S. Tomishima, M. Tsukude, IEEE Journal of Solid-State Circuits Low-power ElectronicsNon-volatile MemoryElectrical EngineeringEngineeringVlsi Design	1995	40
Leakage mechanism due to floating body and countermeasure on dynamic retention mode of SOI-DRAM Fukashi Morishita, K. Suma, Masakazu Hirose, Hardware SecurityNon-volatile MemoryElectrical EngineeringCell TransistorEngineering	2002	32
A Scalable Massively Parallel Processor for Real-Time Image Processing Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, IEEE Journal of Solid-State Circuits EngineeringMultimedia ProcessorComputer ArchitectureSystem-level DesignDouble Frequency	2011	31
A 34-ns 16-Mb DRAM with controllable voltage down-converter Hideto Hidaka, Kazutami Arimoto, K. Hirayama, IEEE Journal of Solid-State Circuits Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignHigh-speed 16-Mb Dram	1992	28
Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors Hiroyuki Kondo, Mamoru Sakugawa, Hayato Fujiwara, IEEE Journal of Solid-State Circuits Heterogeneous ComputingEngineeringComputer ArchitectureSystem-level DesignEmbedded Systems	2008	25
A 34 ns 256 Mb DRAM with boosted sense-ground scheme M. Asakura, T. Ohishi, M. Tsukude, EngineeringMemory DesignEmerging Memory TechnologyComputer ArchitectureMulti-channel Memory Architecture	2002	23

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