IEEE Journal of Solid-State Circuits · 1989 · 69 citations · 6 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureFault-tolerant ComputingMicroelectronicsError Control CodingError CorrectionError DetectionError-correcting CodesMemory Subsystem DesignSelf-checking CircuitsError Correction CodesError Detection CircuitsHamming CodesParity BitsParity Check CodesParity CheckingSoft Error CorrectionSoft Error Mitigation
An error checking and correcting (ECC) technique that checks multiple cell data simultaneously and allows fast column access is described. The ECC circuit is optimized with respect to the increase in the chip area and the access-time penalty, and can be applied to a 16-Mbit DRAM with 20% chip area increase and less access-time penalty. The soft error rate has been estimated to be about 100 times smaller than that of the basic horizontal-vertical parity-code ECC technique.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Circuit technologies for 16Mb DRAMs
T. Mano, Takeshi Matsumura, J. Yamada et al. · 1987 · 37 citations
Engineering, Computer Engineering, Electrical Engineering +14
A 4-Mbit DRAM with 16-bit concurrent ECC
T. Yamada, H. Kotani, J. Matsushima et al. · IEEE Journal of Solid-State Circuits · 1988 · 28 citations
Engineering, Computer Engineering, Electrical Engineering +13