K. Dosaka

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture

Haruhiko Noda, Kazunari Inoue, M. Kuroiwa et al. · IEEE Journal of Solid-State Circuits · 2005 · 104 citations

Engineering, Vlsi Design, Small Cell Size +17

A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS

Isamu Hayashi, Teruhiko Amano, Naoya Watanabe et al. · IEEE Journal of Solid-State Circuits · 2013 · 83 citations

Low-power Electronics, Electrical Engineering, Image Sensor +11

Analysis of coupling noise between adjacent bit lines in megabit DRAMs

Y. Konishi, M. Kumanoya, H. Yamasaki et al. · IEEE Journal of Solid-State Circuits · 1989 · 58 citations

Electrical Engineering, Adjacent Bit Lines, Different Bit-line Structures +14

A multimedia 32 b RISC microprocessor with 16 Mb DRAM

Toshihisa Shimizu, J. Korematu, M. Satou et al. · 2002 · 56 citations

System On Chip, Engineering, B Microprocessor +13

A 40GOPS 250mW massively parallel processor based on matrix architecture

M. Nakajima, Haruhiko Noda, K. Dosaka et al. · 2006 · 52 citations

Engineering, Matrix Processing Engine, Computer Architecture +16