Naoya Watanabe - Concepedia

Author

Naoya Watanabe

National Institute of Advanced Industrial Science and Technology ORCID

Also Known As

N Watanabe, N. WATANABE, N. Watanabe, Naoya WATANABE, Naoya Watanabe, Watanabe, N.

204

Publications

1.1K

Citations

H-Index

Concepts

All Affiliations

National Institute of Advanced Industrial Science and Technology Kyushu Institute of Technology NTT (Japan)Kobe University Kyushu University

About

Naoya Watanabe is an author at National Institute of Advanced Industrial Science and Technology specializing in engineering, microelectronics, and materials science.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	16	37	749
2	Applied Physics	12	22	344
3	Health Sciences	1	1	15
4	Natural Sciences	1	1	14
5	Chemistry	1	1	22

Naoya Watanabe

Publications

790

Citations

H-Index

Page 1

	Year	Citations
A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, IEEE Journal of Solid-State Circuits Low-power ElectronicsElectrical EngineeringImage SensorEngineeringVlsi Design	2013	83
Characteristics of a cell multiplexer for bursty ATM traffic Masanori Hirano, Naoya Watanabe Bursty Input TrafficAdmission ControlNetwork FlowsEngineeringMultiplexing	2003	79
13.6 A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM Koji Nii, Teruhiko Amano, Naoya Watanabe, EngineeringTable EntriesComputer ArchitectureTcam Test-chipImage Sensor	2014	59
Fabrication of Back-Side Illuminated Complementary Metal Oxide Semiconductor Image Sensor Using Compliant Bump Naoya Watanabe, Isao Tsunoda, Takayuki Takao, Japanese Journal of Applied Physics Sensor TechnologyElectrical EngineeringWafer Scale ProcessingEngineeringPhotoelectric Sensor	2010	38
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices Takuji Miki, Makoto Nagata, Hiroki Sonoda, IEEE Journal of Solid-State Circuits Hardware TrojanEngineeringInformation SecuritySide-channel AttackCmos Cryptographic Chip	2020	30
Room-Temperature Cu–Cu Bonding in Ambient Air Achieved by Using Cone Bump Naoya Watanabe, Tanemasa Asano Applied Physics Express Materials EngineeringMaterials ScienceCone BumpEngineeringNanomaterials	2010	22
Wafer-level compliant bump for three-dimensional LSI with high-density area bump connections Naoya Watanabe, Takeaki Kojima, Tanemasa Asano EngineeringMechanical EngineeringComputer ArchitectureInterconnect (Integrated Circuits)Wafer Scale Processing	2006	22
Traffic characteristics and a congestion control scheme for an ATM network Miki Hirano, Naoya Watanabe International Journal of Digital & Analog Communication Systems Admission ControlEngineeringEdge ComputingNetwork Traffic ControlCongestion Control Scheme	1990	21
Renovating a house to aim for net-zero energy, thermal comfort, energy self-consumption and behavioural adaptation: A method proposed for ENEMANE HOUSE 2017 Reina Oki, Yugo Tsuneoka, Shingo Yamaguchi, Energy and Buildings	2019	20
3-D CMOS Chip Stacking for Security ICs Featuring Backside Buried Metal Power Delivery Networks With Distributed Capacitance Kazuki Monta, Hiroki Sonoda, Takaaki Okidono, IEEE Transactions on Electron Devices EngineeringComputer Architecture3-D StacksIntegrated CircuitsPower Delivery Network	2021	20

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