M. Kumanoya - Concepedia

Author

M. Kumanoya

Mitsubishi Electric (Japan)

Also Known As

M. Kumanoya, Masaki Kumanoya

Publications

279

Citations

H-Index

Concepts

All Affiliations

Mitsubishi Electric (Japan)Mitsubishi Group (Japan)Mitsubishi Corporation (United States)

About

M. Kumanoya is an author at Mitsubishi Electric (Japan) specializing in engineering, computer engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	9	9	235
2	Computer Engineering	9	9	235
3	Electrical Engineering	4	4	110
4	Computer Science	3	3	84
5	Applied Physics	1	1	58

M. Kumanoya

Publications

235

Citations

H-Index

Page 1

	Year	Citations
Analysis of coupling noise between adjacent bit lines in megabit DRAMs Y. Konishi, M. Kumanoya, H. Yamasaki, IEEE Journal of Solid-State Circuits Electrical EngineeringAdjacent Bit LinesDifferent Bit-line StructuresEngineeringEmerging Memory Technology	1989	58
A multimedia 32 b RISC microprocessor with 16 Mb DRAM Toshihisa Shimizu, J. Korematu, M. Satou, System On ChipEngineeringB MicroprocessorComputer DesignMulti-channel Memory Architecture	2002	56
A 90ns 1Mb DRAM with multi-bit test mode M. Kumanoya, K. Fujishima, K. Tsukamoto, Hardware SecurityMulti-bit Test ModeMemory ArchitectureEngineeringMemory Design	1985	24
A reliable 1-Mbit DRAM with a multi-bit-test mode M. Kumanoya, K. Fujishima, Hiroshi Miyatake, IEEE Journal of Solid-State Circuits Electrical EngineeringEffective Redundancy CircuitEngineeringMem TestingComputer Engineering	1985	20
A 100-MHz 4-Mb cache DRAM with fast copy-back scheme K. Dosaka, Y. Konishi, K. Hayano, IEEE Journal of Solid-State Circuits Non-volatile MemoryEngineeringMemory DesignEmerging Memory TechnologyComputer Architecture	1992	19
A 100 MHz 4 Mb cache DRAM with fast copy-back scheme K. Dosaka, Y. Konishi, K. Hayano, Non-volatile MemoryEngineeringMemory Design4-Mb CdramEmerging Memory Technology	2003	18
A delay-locked loop and 90-degree phase shifter for 100 Mbps double data rate memories Tsutomu Yoshimura, Y. Nakase, Naoya Watanabe, Recent High-speed DramsEngineeringDouble Data RateClock Recovery90-Degree Phase Shifter	2002	17
A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode Y. Konishi, K. Dosaka, Takanori Komatsu, IEEE Journal of Solid-State Circuits Electrical EngineeringMemory ArchitectureEngineeringMemory DesignData Retention	1990	13
A 90 MHz 16 Mbit system integrated memory with direct interface to CPU K. Dosaka, Akira Yamazaki, Naoya Watanabe, Hardware SecuritySystem On ChipSystem Integrated MemoryEngineeringMhz 16	2002	10

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