A 90ns 1Mb DRAM with multi-bit test mode

Abstract

A 1Mb DRAM using a half Vcc biased memory cell with a reduced electric field of 2MV/cm will be reported. A shared sense amplifier design and a continous nibble mode are also included. Additionally, a test pin allows testing as a 256K×4 memory. Die is 65mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .