N. Sakashita - Concepedia

Author

N. Sakashita

Mitsubishi Electric (Japan)

Also Known As

N. Sakashita, Narumi Sakashita

Publications

352

Citations

H-Index

Concepts

All Affiliations

Mitsubishi Electric (Japan)Mitsubishi Group (Japan)Mitsubishi Electric (United States)

About

N. Sakashita is an author at Mitsubishi Electric (Japan) specializing in engineering, computer engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	11	11	333
2	Computer Engineering	11	11	333
3	Computer Science	4	4	164
4	Education	1	1	12
5	Health Sciences	1	1	79

N. Sakashita

Publications

333

Citations

H-Index

Page 1

	Year	Citations
A built-in self-test for ADC and DAC in a single-chip speech CODEC E. Teraoka, T. Kengaku, Ikuo Yasui, EngineeringAnalog DesignAnalog VerificationBist DesignSpeech Recognition	2002	79
Fuzzy inference and fuzzy inference processor Kazuo Nakamura, N. Sakashita, Y. Nitta, IEEE Micro Artificial IntelligenceFuzzy SystemsEngineeringFuzzy ControlFuzzy Modeling	1993	62
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme Hitoshi Tanaka, Masakazu Aoki, T. Sakata, IEEE Journal of Solid-State Circuits Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignCircuit System	1999	57
A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture N. Sakashita, Y. Nitta, K. Shimomura, IEEE Journal of Solid-State Circuits Electrical EngineeringEngineeringVlsi DesignSingle DramComputer Engineering	1996	23
A 1-V 46-ns 16-Mb SOI-DRAM with body control technique K. Shimomura, H. Shimano, N. Sakashita, IEEE Journal of Solid-State Circuits Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignHigh Speed	1997	21
Approaches to extra low voltage DRAM operation by SOI-DRAM T. Eimori, T. Oashi, Fukashi Morishita, IEEE Transactions on Electron Devices Hardware SecurityLow-power ElectronicsElectrical EngineeringModified Mesa IsolationEngineering	1998	20
16 Mb DRAM/SOI technologies for sub-1 V operation T. Oashi, T. Eimori, Fukashi Morishita, Low-power ElectronicsDual Gate CmosElectrical EngineeringEngineeringVlsi Design	2002	18
A built-in self-test circuit with timing margin test function in a 1 Gbit synchronous DRAM N. Sakashita, F. Okuda, K. Shimomura, Gbit Synchronous DramEngineeringVlsi DesignBuilt-in Self-test CircuitMem Testing	2002	15
A 1.6 GB/s data-rate 1 Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture Y. Nitta, N. Sakashita, K. Shimomura, Gb Synchronous DramEngineeringSingle DramComputer ArchitectureComputer Engineering	2002	15
Built-in self-test in a 24 bit floating point digital signal processor N. Sakashita, Hiroko Sawai, E. Teraoka, EngineeringVlsi DesignMeasurementMem TestingComputer Architecture	2002	12

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