A built-in self-test circuit with timing margin test function in a 1 Gbit synchronous DRAM

Abstract

This paper describes the implementation of a BIST circuit with timing margin test functions to a 200 MHz 1 Gbit synchronous DRAM. 220 ps-resolution timing signals with up to 80 ns cycle time are generated by a phase-locked loop (PLL) circuit and a delayed timing generator. These timing signals are used not only as actual control signals but also as reference signals in an AC timing comparator. The entire BIST circuit, which includes 20/spl times/4 bit LFSRs, occupies only 0.8% of the chip area. A cost evaluation of the BIST shows that the technology is effective for 64 Mbit high-speed DRAMs and beyond.