A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations

Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, +13

Non-volatile MemoryEngineeringMemory DesignEmerging Memory TechnologyComputer Architecture +15

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations

Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, +13

IEEE Journal of Solid-State Circuits

Non-volatile MemoryElectrical EngineeringEngineeringVlsi DesignEmerging Memory Technology +13

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues

Satoshi Ishikura, M. Kurumada, T. Terano, +11

IEEE Journal of Solid-State Circuits

Electrical EngineeringAccess TimeEngineeringMemory DesignMemory Architecture +12

Observation of Cu-NQR in Bi2Sr2(Ca1−Y )Cu2O8+δ

T. Oashi, K. Kumagai, Yasuyuki Nakajima, +2

Physica C Superconductivity

Inorganic ChemistryEngineeringSuperconductivityQuantum MaterialsApplied Physics +3

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

K. Suma, T. Tsuruda, Hideto Hidaka, +11

IEEE Journal of Solid-State Circuits

Low-power ElectronicsElectrical EngineeringCmos/simox TechnologyData Retention TimeVlsi Design +10

Leakage mechanism due to floating body and countermeasure on dynamic retention mode of SOI-DRAM

Fukashi Morishita, K. Suma, Masakazu Hirose, +7

Hardware SecurityNon-volatile MemoryElectrical EngineeringCell TransistorEngineering +12

Superconductivity and magnetism of Bi2Sr2CaCu2O Effect of quenching and pulverization

Takekazu Ishida, Kenneth T. Koga, S. Nakamura, +6

Physica C Superconductivity

Materials ScienceMagnetismSuperconducting MaterialHigh-tc SuperconductivityEngineering +6

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique

K. Shimomura, H. Shimano, N. Sakashita, +10

IEEE Journal of Solid-State Circuits

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignHigh Speed +9

Approaches to extra low voltage DRAM operation by SOI-DRAM

T. Eimori, T. Oashi, Fukashi Morishita, +12

IEEE Transactions on Electron Devices

Hardware SecurityLow-power ElectronicsElectrical EngineeringModified Mesa IsolationEngineering +8

16 Mb DRAM/SOI technologies for sub-1 V operation

T. Oashi, T. Eimori, Fukashi Morishita, +12

Low-power ElectronicsDual Gate CmosElectrical EngineeringEngineeringVlsi Design +9