2007 · 66 citations · 7 references
EngineeringComputer EngineeringComputer ScienceLow-power DesignMicroelectronicsSemiconductor DevicesEmbedded Memory BlocksLeakage Power ReductionMemory DevicesMemory Subsystem DesignLow-power Cmos DesignLow-power Embedded DesignLow-power Embedded SystemsLow-power Memory ArchitectureMemory Array ArchitectureMemory Circuit DesignStatic Random-access Memory DesignUltra-low-power Cmos
A 512kb SRAM module is implemented in a 45nm low-standby-power CMOS with variation-tolerant assist circuits against process and temperature. A passive resistance is introduced to the read assist circuit and a divided V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> line is adopted in the memory array to assist the write. Two SRAM cells with areas of 0.245mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 0.327mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> are fabricated. Measurements show that the SNM exceeds 120mV and the write margin improves by 15% in the worst PVT condition.
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Variability in sub-100nm SRAM designs
R. Heald, P. Wang · 2005 · 156 citations
Engineering, Computer Engineering, Electrical Engineering +17