A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> We propose a new 2-port SRAM with a single read bit line (SRBL) eight transistors (8T) memory cell for a 45 nm system-on-a-chip (SoC). Access time tends to be slower as a fabrication is scaled down because of threshold voltage (<formula><tex>$V_{\rm t}$</tex></formula>) random variations. A Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (R/W) access at the same row by using DBSA with the SRBL-8T cell. A rise of the storage node causes misreading. A Read End detecting Replica circuit (RER) and a Local read bit line Dummy Capacitance (LDC) are introduced to solve this issue. A 128 bit lines—512 word lines 64 kb 2-port SRAM macro using these schemes was fabricated by a 45 nm bulk CMOS low-standby-power (LSTP) CMOS process technology <citerefgrp><citeref refid="ref1"/></citerefgrp>. The memory cell size is 0.597 <formula formulatype="inline"><tex>$\mu{\hbox {m}}^{2}$</tex></formula>. This 2-port SRAM macro achieves 7 times faster access time without misreading. </para>