16 Mb DRAM/SOI technologies for sub-1 V operation

T. Oashi, T. Eimori, Fukashi Morishita, T. Iwamatsu, Yutaro Yamaguchi, F. Okuda, K. Shimomura, H. Shimano, N. Sakashita, Kazutami Arimoto,

2002 · 18 citations · 0 references

Concepts

Abstract

Extra low voltage DRAM/SOI technologies were developed using (1) modified MESA isolation without parasitic MOS operation, (2) dual gate CMOS for low Vth control, (3) optimized layout using both body-tied and floating body MOSFETs, and (4) reduced Cb/Cs ratio. Completely redesigned low voltage scheme 16 MDRAM/SOI was successfully realized and functional operation was obtained at very low supply voltage below 1 V.