N. Kepler

Gate engineering for deep-submicron CMOS transistors

Bin Yu, Dong-Hyuk Ju, Wen‐Chin Lee et al. · IEEE Transactions on Electron Devices · 1998 · 78 citations

Engineering, Electrical Engineering, Electronic Materials +16

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

E. Leobandung, H. Nayakama, D. Mocuta et al. · 2005 · 65 citations

Engineering, Computer Engineering, Electrical Engineering +17

Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies

L.T. Su, John Pellerin, Shih-Fen Huang et al. · 2005 · 63 citations

Engineering, Computer Engineering, Electrical Engineering +17

Impact of nitrogen (N/sub 14/) implantation into polysilicon gate on high-performance dual-gate CMOS transistors

Bin Yu, Dong-Hyuk Ju, N. Kepler et al. · IEEE Electron Device Letters · 1997 · 20 citations

Engineering, Electrical Engineering, Implant Imaging +16

Advantages and challenges of high performance CMOS on SOI

M.M. Pelella, W. Maszara, S. Sundararajan et al. · 2002 · 16 citations

Engineering, Electrical Engineering, Microelectronics +16