Shih-Fen Huang

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

Haining Yang, R. Malik, Y. Li et al. · 2005 · 142 citations

Engineering, Electrical Engineering, Manufacturing Engineering +11

High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering

V. Chan, R. Rengarajan, N. Rovedo et al. · 2004 · 76 citations

Engineering, Electrical Engineering, Microelectronics +16

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

E. Leobandung, H. Nayakama, D. Mocuta et al. · 2005 · 65 citations

Engineering, Computer Engineering, Electrical Engineering +17

Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies

L.T. Su, John Pellerin, Shih-Fen Huang et al. · 2005 · 63 citations

Engineering, Computer Engineering, Electrical Engineering +17

Proton-ELISA: Electrochemical immunoassay on a dual-gated ISFET array

Duane S. Juang, Ching-Hui Lin, Ching-Hui Lin et al. · Biosensors and Bioelectronics · 2018 · 52 citations

Engineering, Bioengineering, Biotechnology +14