Shih-Fen Huang

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

Haining Yang, R. Malik, Y. Li et al. · 2005 · 142 citations

Electrical Engineering, Physical Design (Electronics), Engineering +13

High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering

V. Chan, R. Rengarajan, N. Rovedo et al. · 2004 · 76 citations

High Speed 45Nm, Electrical Engineering, Gate Length +15

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

E. Leobandung, H. Nayakama, D. Mocuta et al. · 2005 · 65 citations

Electrical Engineering, Engineering, Vlsi Design +15

Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies

L.T. Su, John Pellerin, Shih-Fen Huang et al. · 2005 · 63 citations

Engineering, Vlsi Design, Silicon On Insulator +16

High performance 50 nm CMOS devices for microprocessor and embedded processor core applications

Shih-Fen Huang, Chih‐Yung Lin, Yu-Shyang Huang et al. · 2002 · 40 citations

Processor Core Applications, Engineering, Vlsi Design +16