Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies

Abstract

An optimized 4-way stress integration on partially-depleted SOI (PD-SOI) CMOS is presented. An embedded-SiGe process and a compressive-stressed liner film are used to induce compressive strain in the PMOS (PMOS "stressors"). A stress memorization process and a tensile-stressed liner film are used to induce tensile strain in the NMOS (NMOS "stressors"). With optimization, the different stress techniques are highly compatible and additive to each other, improving PMOS and NMOS saturation drive current by 53% and 32%, respectively. This improvement results in 40% higher product speed. To demonstrate the extendibility for future transistor nodes the stress improvements were increased further resulting in record PMOS performance of IDSAT=860muA/mum at 200nA IOFF (self-heating corrected) and 1V. The stress techniques are proven in AMD's 90nm manufacturing processes, and have been scaled for use in 65nm manufacturing