Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging

John H. Lau, Ming Li, Dewen Tian, +19

IEEE Transactions on Components Packaging and Manufacturing Technology

Electrical EngineeringChip-scale PackageEngineeringAdvanced Packaging (Semiconductors)Wafer Scale Processing +13

Targeted Disruption of β-Arrestin 2-Mediated Signaling Pathways by Aptamer Chimeras Leads to Inhibition of Leukemic Cell Growth

Jonathan W. Kotula, Jin‐Peng Sun, Margie Li, +5

PLoS ONE

Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration

Cheng-Ta Ko, John H. Lau, Ming Li, +29

IEEE Transactions on Components Packaging and Manufacturing Technology

EngineeringEnergy EfficiencyComputer ArchitectureInterconnect (Integrated Circuits)Advanced Packaging (Semiconductors) +14

Warpage Measurements and Characterizations of Fan-Out Wafer-Level Packaging With Large Chips and Multiple Redistributed Layers

John H. Lau, Ming Li, Lei Yang, +16

IEEE Transactions on Components Packaging and Manufacturing Technology

EngineeringMechanical EngineeringFowlp FabricationIntegrated CircuitsWafer Scale Processing +17

Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging

John H. Lau, Ming Li, Dewen Tian, +16

Electrical EngineeringChip SizeEngineeringChip-scale PackageAdvanced Packaging (Semiconductors) +13

Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution Layers (RDLs)

John H. Lau, Ming Li, Nelson Fan, +23

Journal of Microelectronics and Electronic Packaging

EngineeringComputer ArchitectureWafer Scale ProcessingAdvanced Packaging (Semiconductors)Materials Fabrication +15

Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration

Cheng-Ta Ko, Chieh-Lin Chang, Jhih-Yuan Pan, +30

EngineeringEnergy EfficiencyComputer ArchitectureAdvanced Packaging (Semiconductors)Heterogeneous Integration +16

Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration

Cheng-Ta Ko, Henry Yang, John H. Lau, +24

Journal of Microelectronics and Electronic Packaging

Materials ScienceAdvanced PackagingElectrical EngineeringEngineeringAdvanced Packaging (Semiconductors) +13

Reliability of Fan-Out Wafer-Level Heterogeneous Integration

John H. Lau, Ming Li, Yang Lei, +23

Journal of Microelectronics and Electronic Packaging

EngineeringEnergy EfficiencyPower Electronic SystemsWafer Scale ProcessingAdvanced Packaging (Semiconductors) +15

Fan-Out Wafer-Level Packaging for Heterogeneous Integration

John H. Lau, Zhang Li, K. H. Tan, +25

3D Ic ArchitectureElectrical EngineeringNew Assembly ProcessEngineeringChip-scale Package +12