S. Pauliac - Concepedia

Author

S. Pauliac

Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Also Known As

Pauliac, S., S. Pauliac, Sebastien Pauliac, Sébastien Pauliac

Publications

341

Citations

H-Index

Concepts

All Affiliations

Commissariat à l'Énergie Atomique et aux Énergies Alternatives Laboratoire d'Électronique des Technologies de l'Information CEA Grenoble Centre National de la Recherche Scientifique Institut de Microélectronique, Electromagnétisme et Photonique

About

S. Pauliac is an author at Commissariat à l'Énergie Atomique et aux Énergies Alternatives specializing in applied physics, engineering, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	10	10	275
2	Applied Physics	10	10	275
3	Electrical Engineering	9	9	264
4	Computer Engineering	2	2	28
5	Materials Engineering	1	1	13

S. Pauliac

Publications

315

Citations

H-Index

Page 1

	Year	Citations
15nm-diameter 3D stacked nanowires with independent gates operation: &#x03A6;FET C. Dupré, A. Hubert, Stéphane Bécu, Co-processed FinfetEngineeringIntegrated CircuitsIndependent-gate FinfetSemiconductor Device	2008	111
Low-Crosstalk Fabrication-Insensitive Echelle Grating Demultiplexers on Silicon-on-Insulator Corrado Sciancalepore, R. J. Lycett, Jacques-Alexandre Dallery, IEEE Photonics Technology Letters Optical MaterialsEngineeringDevice IntegrationIntegrated PhotonicsOptoelectronic Devices	2014	43
A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with gate-all-around or independent gates (Φ-Flash), suitable for full 3D integration. A. Hubert, Emmanuel Nowak, K. Tachi, HAL (Le Centre pour la Communication Scientifique Directe)	2009	40
Line edge roughness characterization with a three-dimensional atomic force microscope: Transfer during gate patterning processes J. Thiault, J. Foucher, J.H. Tortai, Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena EngineeringElectron-beam LithographyMicroscopySilicon On InsulatorNanotribology	2005	31
Oxidation of Suspended Stacked Silicon Nanowire for Sub-10nm Cross-Section Shape Optimization Alexandre Hubert, Jean-Philippe Colonna, Stéphane Bécu, ECS Transactions EngineeringThermal OxidationSilicon On InsulatorInterconnect (Integrated Circuits)Semiconductor Device	2008	17
A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (&#x03C6;-Flash), suitable for full 3D integration A. Hubert, E. Nowak, K. Tachi, EngineeringDevice IntegrationNanodevicesEmerging Memory TechnologyCrystalline Nanowires	2009	16
High-Resolution Hybrid Lithography with Negative Tone Chemically Amplified Resists S. Landis, S. Pauliac, J. Saint-Pol, Japanese Journal of Applied Physics Materials ScienceMaterials EngineeringElectrical EngineeringOptical MaterialsEngineering	2004	13
Scalability of split-gate charge trap memories down to 20nm for low-power embedded memories L. Masoero, G. Molas, F. Brun, Non-volatile MemoryEngineeringEmerging Memory TechnologyComputer ArchitectureSemiconductor Device	2011	12
Hybrid lithography process for nano-scale devices S. Pauliac, S. Landis, J. Foucher, Microelectronic Engineering Materials ScienceWafer Scale ProcessingEngineeringNanoengineeringBeam Lithography	2006	11
(Invited) Evaluation of Stacked Nanowires Transistors for CMOS: Performance and Technology Opportunities L. Gaben, Sylvain Barraud, Marie-Pierre Samson, ECS Transactions EngineeringVlsi DesignDevice Effective WidthNanocomputingSemiconductor Device	2016	11

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