S. Pauliac

15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET

C. Dupré, A. Hubert, Stéphane Bécu et al. · 2008 · 111 citations

Co-processed Finfet, Engineering, Integrated Circuits +17

Low-Crosstalk Fabrication-Insensitive Echelle Grating Demultiplexers on Silicon-on-Insulator

Corrado Sciancalepore, R. J. Lycett, Jacques-Alexandre Dallery et al. · IEEE Photonics Technology Letters · 2014 · 43 citations

Optical Materials, Engineering, Device Integration +19

A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with gate-all-around or independent gates (Φ-Flash), suitable for full 3D integration.

A. Hubert, Emmanuel Nowak, K. Tachi et al. · HAL (Le Centre pour la Communication Scientifique Directe) · 2009 · 40 citations

Line edge roughness characterization with a three-dimensional atomic force microscope: Transfer during gate patterning processes

J. Thiault, J. Foucher, J.H. Tortai et al. · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena · 2005 · 31 citations

Engineering, Electron-beam Lithography, Microscopy +22

Oxidation of Suspended Stacked Silicon Nanowire for Sub-10nm Cross-Section Shape Optimization

Alexandre Hubert, Jean-Philippe Colonna, Stéphane Bécu et al. · ECS Transactions · 2008 · 17 citations

Engineering, Thermal Oxidation, Silicon On Insulator +16