Oxidation of Suspended Stacked Silicon Nanowire for Sub-10nm Cross-Section Shape Optimization

Abstract

Suspended, stacked and rounded nanowires with diameters as small as 5nm have been obtained thanks to thermal oxidation. Those structures can be used for novel 3D Gate-All-Around Field Effect Transistor (GAAFET) architectures. As the oxidation rate is strongly affected by the nature of the oxidant, the temperature and the wire curvature, both wet and dry oxidations (at 950{degree sign}C and at 1100{degree sign}C, respectively) have been investigated. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) were used to characterize the shape and the oxidation kinetic of the oxidized Si nanowires compared to planar references.