V. Maffini-Alvaro - Concepedia

Author

V. Maffini-Alvaro

Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Also Known As

Maffini-Alvaro, V., V Maffini-Alvaro, V. Maffini-Alvaro, Virginie Maffini-Alvaro

Publications

961

Citations

H-Index

Concepts

All Affiliations

Commissariat à l'Énergie Atomique et aux Énergies Alternatives CEA Grenoble Laboratoire d'Électronique des Technologies de l'Information STMicroelectronics (France)Institut polytechnique de Grenoble

About

V. Maffini-Alvaro is an author at Commissariat à l'Énergie Atomique et aux Énergies Alternatives specializing in engineering, applied physics, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	17	20	848
2	Applied Physics	17	19	835
3	Electrical Engineering	17	20	848
4	Computer Engineering	2	2	46
5	Materials Engineering	1	1	11

V. Maffini-Alvaro

Publications

919

Citations

H-Index

Page 1

	Year	Citations
Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm Sylvain Barraud, R. Coquand, M. Cassé, IEEE Electron Device Letters Electrical EngineeringSemiconductor DeviceEngineeringDiameter DownNanotechnology	2012	145
15nm-diameter 3D stacked nanowires with independent gates operation: &#x03A6;FET C. Dupré, A. Hubert, Stéphane Bécu, Co-processed FinfetEngineeringIntegrated CircuitsIndependent-gate FinfetSemiconductor Device	2008	111
Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain Sylvain Barraud, V. Lapras, Marie-Pierre Samson, EngineeringInner SpacerIntegrated CircuitsSilicon On InsulatorSemiconductor Device	2016	108
Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack T. Ernst, C. Dupré, Christian Isheden, EngineeringHfo2/tin Gate StackFinfet ProcessSemiconductor MaterialsIntegrated Circuits	2006	61
Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width R. Coquand, Sylvain Barraud, M. Cassé, Electrical EngineeringSi Film ThicknessEngineeringSemiconductor DeviceTechnology Scaling	2012	57
Hydrogen annealing of arrays of planar and vertically stacked Si nanowires E. Dornel, T. Ernst, J.-Ch. Barbé, Applied Physics Letters EngineeringNanodevicesSi NanowiresSilicon On InsulatorSuspended Nanowires	2007	50
A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with gate-all-around or independent gates (Φ-Flash), suitable for full 3D integration. A. Hubert, Emmanuel Nowak, K. Tachi, HAL (Le Centre pour la Communication Scientifique Directe)	2009	40
Relationship between mobility and high-k interface properties in advanced Si and SiGe nanowires K. Tachi, M. Cassé, Doyoung Jang, EngineeringIntegrated CircuitsSilicon On InsulatorSemiconductor DeviceSemiconductor Nanostructures	2009	35
Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width R. Coquand, M. Cassé, Sylvain Barraud, EngineeringIntegrated CircuitsSemiconductor DeviceStrain-induced Performance EnhancementSemiconductors	2012	30
3D nanowire gate-all-around transistors: Specific integration and electrical features C. Dupré, T. Ernst, V. Maffini-Alvaro, Solid-State Electronics Electrical EngineeringEngineeringNanoelectronicsApplied PhysicsNanocomputing	2007	30

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