S. Tanaka

A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure

Akira Umezawa, S. Atsumi, M. Kuriyama et al. · IEEE Journal of Solid-State Circuits · 1992 · 147 citations

Non-volatile Memory, Electrical Engineering, Cell Size +15

A new flash E<sup>2</sup>PROM cell using triple polysilicon technology

F. Masuoka, Masafumi Asano, H. Iwahashi et al. · 1984 · 103 citations

Non-volatile Memory, Miniaturization, Engineering +19

A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology

J. Mori, M. Nagamatsu, M. Hirano et al. · IEEE Journal of Solid-State Circuits · 1991 · 98 citations

Electrical Engineering, Engineering, Vlsi Design +12

A 15-ns 32*32-b CMOS multiplier with an improved parallel structure

M. Nagamatsu, S. Tanaka, J. Mori et al. · IEEE Journal of Solid-State Circuits · 1990 · 87 citations

Electrical Engineering, Engineering, Vlsi Design +14

One-dimensional writing model of n-channel floating gate ionization-injection MOS (FIMOS)

S. Tanaka, M. Ishikawa · IEEE Transactions on Electron Devices · 1981 · 37 citations

Device Modeling, Electrical Engineering, Gate Ionization-injection Mos +13