Eric Ouyang

High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme

Chau-Neng Wu, Dongyang Lin, A. Keshavarzi et al. · 2010 · 105 citations

Finfet Cmos Devices, Electrical Engineering, Engineering +12

A 25-nm gate-length FinFET transistor module for 32nm node

Chang-Yun Chang, Tsung-Lin Lee, C. Wann et al. · 2009 · 62 citations

Low-power Electronics, Electrical Engineering, Engineering +11

CuBOL (Cu-column on BOL) technology: A low cost flip chip solution scalable to high I/O density, fine bump pitch and advanced Si-nodes

S. Movva, Steve Bezuk, Omar Bchir et al. · 2011 · 30 citations

Engineering, Flip Chip Package, Integrated Circuits +20

Strip warpage analysis of a flip chip package considering the mold compound processing parameters

MyoungSu Chae, Eric Ouyang · 2013 · 24 citations

Engineering, Flip Chip Package, Mechanical Engineering +21

Improvement of ELK Reliability in Flip Chip Packages using Bond-on-Lead (BOL) Interconnect Structure

Eric Ouyang, MyoungSu Chae, Seng Guan Chow et al. · IMAPSource Proceedings · 2010 · 22 citations · Full text

Interconnect Structure, Electrical Engineering, Chip-scale Package +15