Porous silica materials as low-k dielectrics for electronic and optical interconnects

A. K. Jain, Svetlana Rogojevic, S. Ponoth, +7

Thin Solid Films

Materials ScienceOptical MaterialsOptical InterconnectsElectronic MaterialsEngineering +8

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

Kangguo Cheng, A. Khakifirooz, P. Kulkarni, +33

Low-power ElectronicsElectrical EngineeringSige RsdEngineeringVlsi Design +10

High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond

Qianlong Liu, M. Vinet, J. Gimbert, +36

Semiconductor TechnologyElectrical EngineeringGate LengthEngineeringVlsi Design +13

Numerical simulation of mass transfer for bubbles in water

S. Ponoth, John B. McLaughlin

Chemical Engineering Science

Bubble DynamicEngineeringHydrodynamic CavitationFluid MechanicsNumerical Simulation +3

Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond

Qijiong Liu, A. Yagishita, N. Loubet, +34

Low-power ElectronicsDevice ModelingElectrical EngineeringUtbb StructureEngineering +13

Processing dependent thermal conductivity of nanoporous silica xerogel films

Anurag Jain, Svetlana Rogojevic, S. Ponoth, +5

Journal of Applied Physics

Materials ScienceMaterials EngineeringSinteringEngineeringNanomaterials +11

The effect of Cu diffusion on the TDDB behavior in a low-k interlevel dielectrics

J. R. Lloyd, Conal E. Murray, S. Ponoth, +2

Microelectronics Reliability

Materials EngineeringElectrical EngineeringElectromigration TechniqueEngineeringDiffusion Resistance +9

UTBB FDSOI transistors with dual STI for a multi-V<inf>t</inf> strategy at 20nm node and below

L. Grenouillet, M. Vinet, J. Gimbert, +39

Electrical EngineeringUtbb Fdsoi TransistorsEngineeringVlsi DesignVlsi Architecture +9

Impact of back bias on ultra-thin body and BOX (UTBB) devices

Q. Liu, F. Monsieur, Arvind Kumar, +39

V BbElectrical EngineeringBiomedical SensorsEngineeringBack Bias +11

Scalability of Extremely Thin SOI (ETSOI) MOSFETs to Sub-20-nm Gate Length

A. Khakifirooz, Kangguo Cheng, A. Reznicek, +11

IEEE Electron Device Letters

Sub-20-nm Gate LengthElectrical EngineeringEngineeringChannel ThicknessSoi Thickness Scaling +11