V.P. Ganesh - Concepedia

Author

V.P. Ganesh

Institute of High Performance Computing

Also Known As

V. Ganesh, V. P. Ganesh, V.P. Ganesh, VP Ganesh, Vivek Ganesh

Publications

363

Citations

H-Index

Concepts

All Affiliations

Institute of High Performance Computing Institute of Microelectronics Infineon Technologies (Singapore)STMicroelectronics (Singapore)STATS ChipPAC (Singapore)

About

V.P. Ganesh is an author at Institute of High Performance Computing specializing in engineering, electronic packaging, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	10	10	259
2	Electrical Engineering	7	7	201
3	Applied Physics	5	5	83
4	Computer Engineering	4	4	145
5	Materials Engineering	3	3	62

V.P. Ganesh

Publications

331

Citations

H-Index

Page 1

	Year	Citations
Three-dimensional system-in-package using stacked silicon platform technology V. Kripesh, Seung Wook Yoon, V.P. Ganesh, IEEE Transactions on Advanced Packaging EngineeringComputer ArchitectureGood DiceDaisy ChainAdvanced Packaging (Semiconductors)	2005	76
Next generation eWLB (embedded wafer level BGA) packaging Yonggang Jin, Xavier Baraton, Seung Wook Yoon,	2010	72
Mechanical characterization of next generation eWLB (embedded wafer level BGA) packaging Seung Wook Yoon, Yaojian Lin, Sharma Gaurav, EngineeringThin EwlbMechanical EngineeringMechanical CharacterizationIntegrated Circuits	2011	32
Numerical Study of Gold Wire Bonding Process on Cu/Low-k Structures A.G.K. Viswanath, Xiaowu Zhang, V.P. Ganesh IEEE Transactions on Advanced Packaging EngineeringSevere Plastic DeformationMechanical EngineeringInterconnect (Integrated Circuits)Numerical Study	2007	30
Reliability Studies of a Through Via Silicon Stacked Module for 3D Microsystem Packaging Seung Wook Yoon, D. Witarsa, S. Yak, EngineeringMicrosystem PackagingMechanical EngineeringReliability EngineeringAdvanced Packaging (Semiconductors)	2006	27
Development of 3-D Stack Package Using Silicon Interposer for High-Power Application Navas Khan, Seung Wook Yoon, A.G.K. Viswanath, IEEE Transactions on Advanced Packaging EngineeringComputer ArchitectureAdvanced Packaging (Semiconductors)Electronic Packaging3D Ic Architecture	2008	24
Optimization of gold wire bonding on electroless nickel immersion gold for high temperature applications Beng Teck Ng, V.P. Ganesh, Charles Lee EngineeringMechanical EngineeringGold WireInterconnect (Integrated Circuits)Advanced Packaging (Semiconductors)	2006	19
Numerical Analysis by 3D Finite Element Wire Bond Simulation on Cu/Low-K Structures A.G.K. Viswanath, Fang Wang, Xiaowu Zhang, Numerical AnalysisEngineeringSevere Plastic DeformationMechanical EngineeringMaterial Simulation	2006	17
Packaging and Assembly of 3-D Silicon Stacked Module for Image Sensor Application Seung Wook Yoon, V.P. Ganesh, S. Lim, IEEE Transactions on Advanced Packaging EngineeringIntegrated CircuitsImage SensorFlip ChipWafer Scale Processing	2008	13
Overview and Emerging Challenges in Wafer Thinning Process for Handheld Applications V.P. Ganesh, Charles Lee IEEE/CPMT International Electronics Manufacturing Technology Symposium EngineeringMechanical EngineeringWafer Thinning ProcessHandheld ApplicationsWafer Scale Processing	2006	11

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