D. Galpin

Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm² 6T-SRAM bitcell

C. Fenouillet-Béranger, J. Todeschini, Jean-Christophe Le-Denmat et al. · 2007 · 61 citations

Engineering, Computer Engineering, Electrical Engineering +15

Analysis of electromigration induced early failures in Cu interconnects for 45nm node

L. Arnaud, F. Cacho, Laurent Doyen et al. · Microelectronic Engineering · 2009 · 21 citations

Engineering, Electrical Engineering, Materials Science +14

32nm node BEOL integration with an extreme low-k porous SiOCH dielectric k=2.3

K. Hamioud, V. Arnal, A. Farcy et al. · Microelectronic Engineering · 2009 · 16 citations

Engineering, Materials Engineering, Materials Science +12

Silicide pre-clean effects on NiPtSi thermal stability for 65nm technologies and beyond

Susana Bonnetier, B. Imbert, M. Hopstaken et al. · Microelectronic Engineering · 2007 · 12 citations

Engineering, Materials Engineering, Materials Science +14

90nm toggle MRAM array with 0.29μm/sup 2/ cells

M. Durlam, T. André, P. Brown et al. · 2005 · 11 citations

Engineering, Computer Engineering, Electrical Engineering +12