Jung-Hwan Choi

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

Uksong Kang, Hoeju Chung, Seongmoo Heo et al. · IEEE Journal of Solid-State Circuits · 2010 · 484 citations

3D Ic Architecture, Electrical Engineering, Engineering +12

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution

Kyomin Sohn, Won-Joo Yun, Reum Oh et al. · IEEE Journal of Solid-State Circuits · 2016 · 60 citations

Hardware Security, Non-volatile Memory, Electrical Engineering +13

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

Kyomin Sohn, Taesik Na, Indal Song et al. · IEEE Journal of Solid-State Circuits · 2012 · 54 citations

Hardware Security, Memory Architecture, Dual-error Detection +12

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

Chang‐Kyo Lee, Yoon-Joo Eom, Jin‐Hee Park et al. · 2017 · 44 citations

Low-power Electronics, Hardware Security, Electrical Engineering +15

Modeling of Power Supply Noise in Large Chips Using the Circuit-Based Finite-Difference Time-Domain Method

Jung-Hwan Choi, Madhavan Swaminathan, N. Do et al. · IEEE Transactions on Electromagnetic Compatibility · 2005 · 40 citations

Electrical Engineering, Physical Design (Electronics), Engineering +15