Indal Song

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

Kyomin Sohn, Taesik Na, Indal Song et al. · IEEE Journal of Solid-State Circuits · 2012 · 55 citations

Engineering, Computer Engineering, Electrical Engineering +16

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

Chang‐Kyo Lee, Yoon-Joo Eom, Jin‐Hee Park et al. · 2017 · 44 citations

Engineering, Computer Engineering, Electrical Engineering +17

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage–Frequency Scaling in LPDDR4 SDRAM

Chang‐Kyo Lee, Jun-Ha Lee, Kiho Kim et al. · IEEE Journal of Solid-State Circuits · 2018 · 19 citations

Engineering, Computer Engineering, Electrical Engineering +14

A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme

Kyomin Sohn, Taesik Na, Indal Song et al. · 2012 · 17 citations

Engineering, Computer Engineering, Computer Science +16

17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs

Won-Joo Yun, Indal Song, Hanki Jeoung et al. · 2015 · 12 citations

Engineering, Computer Engineering, Electrical Engineering +15