S. Brus

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

T. Chiarella, Liesbeth Witters, A. Mercha et al. · Solid-State Electronics · 2010 · 120 citations

Electrical Engineering, Physical Design (Electronics), Engineering +8

Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS

A. Veloso, Geert Hellings, M. J. Cho et al. · 2015 · 52 citations

Engineering, Integrated Circuits, Quantum Engineering +18

(Invited) Vertical Nanowire FET Integration and Device Aspects

A. Veloso, Efrain Altamirano Sánchez, S. Brus et al. · ECS Transactions · 2016 · 49 citations

Low-power Electronics, Electrical Engineering, Physical Design (Electronics) +13

WS<inf>2</inf> transistors on 300 mm wafers with BEOL compatibility

T. Schram, Quentin Smets, Benjamin Groven et al. · 2017 · 40 citations

Materials Science, Semiconductors, Electrical Engineering +14

Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

A. Veloso, Bertrand Parvais, Philippe Matagne et al. · 2016 · 37 citations

Engineering, Nanocomputing, Semiconductor Device +18