Trong Huynh-Bao

The Complementary FET (CFET) for CMOS scaling beyond N3

Julien Ryckaert, P. Schuddinck, Pieter Weckx et al. · 2018 · 206 citations

Finfet Device, Engineering, Vlsi Design +18

Vertical GAAFETs for the Ultimate CMOS Scaling

Dmitry Yakimets, Geert Eneman, P. Schuddinck et al. · IEEE Transactions on Electron Devices · 2015 · 191 citations

Power Consumption, Electrical Engineering, Engineering +13

Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications

A. Veloso, Trong Huynh-Bao, Philippe Matagne et al. · Solid-State Electronics · 2019 · 74 citations

Materials Science, Electrical Engineering, Engineering +7

Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node

Sushil Sakhare, Manu Perumkunnil, Trong Huynh-Bao et al. · 2018 · 62 citations

Last Level Cache, Non-volatile Memory, Electrical Engineering +14

Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond

Trong Huynh-Bao, Julien Ryckaert, Zsolt Tökei et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2017 · 54 citations

Engineering, Vlsi Design, Beol Requirements +18