Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node

TLDR

The increasing complexity of CMOS processing limits SRAM scaling at advanced nodes, making STT‑MRAM a promising candidate for last‑level caches. This paper investigates design‑technology co‑optimization of STT‑MRAM to evaluate its viability as a high‑performance computing last‑level cache while keeping its area to 43.3 % of an equivalent SRAM macro. The authors employ a silicon‑verified compact model and 193 nm single‑patterning to design and analyze the STT‑MRAM at the 5 nm node, optimizing for area, performance, and power. The study demonstrates that STT‑MRAM LLCs at 5 nm achieve sub‑2.5 ns read and sub‑7.1 ns write latencies, provide a comprehensive PPA comparison with SRAM, and deliver increasing energy savings for larger cache sizes with crossover points at 0.4 MB (read) and 5 MB (write).

Abstract

The increased complexity of CMOS transistor processing has led to limited scaling of high density SRAM cell at advanced technology nodes. STT-MRAM appears to be a promising candidate for replacing last level caches (LLC). This paper addresses design technology co-optimization (DTCO) of STT-MRAM technology and analyzes its viability as a LLC (compared to SRAM) for the high performance computing (HPC) domain (while maintaining a constraint of occupying merely 43.3% of SRAM macro area at identical capacities). This is the first study that breaks down a power, performance and area (PPA) comparison between SRAM and STT-MRAM based LLCs at the 5nm node. The STT-MRAM design and analysis is based on a silicon verified compact model and can be realized using 193i single patterning at the 5nm node. Our STT-MRAM design manages to achieve a nominal access latency <;2.5ns and <;7.1ns for read and write operations respectively. We also observe a clear and significant trend of increasing energy gains with respect to SRAM for increasing LLC sizes with the crossover points for STT-MRAM read and write operations at 0.4MB and 5MB respectively.