Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node

Sushil Sakhare, Manu Perumkunnil, Trong Huynh-Bao, +14

Last Level CacheNon-volatile MemoryElectrical EngineeringEngineeringVlsi Design +12

Vertical device architecture for 5nm and beyond: Device & circuit implications

A. V-Y. Thean, Dmitry Yakimets, Trong Huynh-Bao, +16

EngineeringVlsi DesignLayout EfficiencyIntegrated CircuitsDevice Density +16

A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs

Trong Huynh-Bao, Sushil Sakhare, Dmitry Yakimets, +5

IEEE Transactions on Electron Devices

Wide-bandgap SemiconductorEngineeringVlsi DesignEmerging Memory TechnologyLateral Gaa Transistors +17

DTCO at N7 and beyond: patterning and electrical compromises and opportunities

Julien Ryckaert, Praveen Raghavan, P. Schuddinck, +14

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

EngineeringVlsi DesignVertical TransistorComputer ArchitectureAggressive Pitch +14

Solving the BEOL compatibility challenge of top-pinned magnetic tunnel junction stacks

Johan Swerts, Enlong Liu, Sébastien Couet, +16

Magnetic PropertiesEngineeringPinning LayerMagnetic MaterialsMagnetoresistance +15

Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs

Trong Huynh-Bao, Julien Ryckaert, Sushil Sakhare, +4

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

EngineeringVlsi DesignComputer ArchitectureSemiconductor DevicePhysical Design (Electronics) +14

Design Technology co-optimization for N10

Julien Ryckaert, Prasanth Raghavan, Rogier Baert, +25

EngineeringVlsi DesignDesign-technology Co-optimizationAccelerated DesignComputer Architecture +19

Design technology co-optimization for a robust 10nm Metal1 solution for logic design and SRAM

B. Vandewalle, Bharani Chava, Sushil Sakhare, +2

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

Computational LithographyEngineeringVlsi DesignElectron-beam LithographyElectronic Design +20

Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems

Sushil Sakhare, Trong Huynh-Bao, Siddharth Rao, +6

Non-volatile MemoryEngineeringEmerging Memory TechnologyComputer ArchitectureStt-mram Design +16

<i>J</i> _SWof 5.5 MA/cm² and RA of 5.2-Ω · μm² STT-MRAM Technology for LLC Application

Sushil Sakhare, Siddharth Rao, Manu Perumkunnil, +6

IEEE Transactions on Electron Devices

SpintronicsElectrical EngineeringTechnology TradeoffEngineeringNon-volatile Memory +13