Sushil Sakhare

Enablement of STT-MRAM as last level cache for the high performance computing domain at the 5nm node

Sushil Sakhare, Manu Perumkunnil, Trong Huynh-Bao et al. · 2018 · 62 citations

Last Level Cache, Non-volatile Memory, Electrical Engineering +14

Vertical device architecture for 5nm and beyond: Device & circuit implications

A. V-Y. Thean, Dmitry Yakimets, Trong Huynh-Bao et al. · 2015 · 49 citations

Engineering, Vlsi Design, Layout Efficiency +18

A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs

Trong Huynh-Bao, Sushil Sakhare, Dmitry Yakimets et al. · IEEE Transactions on Electron Devices · 2015 · 35 citations

Wide-bandgap Semiconductor, Engineering, Vlsi Design +19

DTCO at N7 and beyond: patterning and electrical compromises and opportunities

Julien Ryckaert, Praveen Raghavan, P. Schuddinck et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2015 · 32 citations

Engineering, Vlsi Design, Vertical Transistor +16

Solving the BEOL compatibility challenge of top-pinned magnetic tunnel junction stacks

Johan Swerts, Enlong Liu, Sébastien Couet et al. · 2017 · 29 citations

Magnetic Properties, Engineering, Pinning Layer +17