B. Woolery

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

Peng Bai, C. Auth, S. Balakrishnan et al. · 2005 · 230 citations

Electrical Engineering, Physical Design (Electronics), Engineering +15

Erratic fluctuations of sram cache vmin at the 90nm process technology node

M. Agostinelli, J. Hicks, Jianzhong Xu et al. · 2006 · 116 citations

Hardware Security, Non-volatile Memory, Electrical Engineering +15

Effect of BTI Degradation on Transistor Variability in Advanced Semiconductor Technologies

Sangwoo Pae, J. Maiz, C. Prasad et al. · IEEE Transactions on Device and Materials Reliability · 2008 · 85 citations

Engineering, Technology Scales, Advanced Semiconductor Technologies +17

Reliability characterization of 32nm high-K and Metal-Gate logic transistor technology

Sangwoo Pae, Ashwin Ashok, T. Ghani et al. · 2010 · 59 citations

Reliability, Electrical Engineering, Reliability Engineering +10

Gate dielectric TDDB characterizations of advanced High-k and metal-gate CMOS logic transistor technology

Sangwoo Pae, C. Prasad, S. Ramey et al. · 2012 · 18 citations

Electrical Engineering, Engineering, Vlsi Design +12