Laertis Economikos

High performance 14nm SOI FinFET CMOS technology with 0.0174µm<sup>2</sup> embedded DRAM and 15 levels of Cu metallization

C-H. Lin, B. Greene, J. Cai et al. · 2014 · 128 citations

Investigation of CVD SiCOH low-k time-dependent dielectric breakdown at 65nm node technology

F. Chen, Kaushik Chanda, Inderbir S. Gill et al. · 2005 · 42 citations

Materials Science, Tddb Degradation, Electrical Engineering +14

Electrical test of multichip substrates

Laertis Economikos, Thomas F. Morrison, Frank Crnic · IEEE Transactions on Components Packaging and Manufacturing Technology Part B · 1994 · 33 citations

Engineering, Electrical Test, Integrated Circuits +17

High performance bulk planar 20nm CMOS technology for low power mobile applications

Huiling Shang, S. Jain, E. Josse et al. · 2012 · 26 citations

Low-power Electronics, High Density, Electrical Engineering +14

Integrated electro-chemical mechanical planarization (Ecmp) for future generation device technology

Laertis Economikos, X. Wang, X. Sakamoto et al. · 2004 · 25 citations

Engineering, Mechanical Engineering, Electronic Design +19