2023 · 13 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureEdge ComputingLow-power DesignEdge ArchitectureEdge Artificial IntelligenceEdge DevicesEnergy-efficient Embedded SystemsMemory Subsystem DesignPower ManagementArea EfficiencyCmos ScalingConvolutionEdge Ai InferenceEdge InferenceEnergy-efficient Edge ComputingEnergy-efficient Memory DesignPower-efficient Memory Design
An energy-efficient and high-density first-ever Read Only Memory (ROM) based compute-in-memory (CIM) design for edge AI inference is demonstrated featuring 1) MultiLevel-Cell (MLC) using standard via-programed ROM bitcell; 2) Source-Line PMOS current driving; 3) Auto-scaling diode-connected current-to-voltage (I2V) converters; 4) 3-b ADC with ROM-based VREF generation; 5) Early termination of convolution operation for power savings. A 65nm CMOS prototype achieves a state-of-the-art energy efficiency of ~66.21 to 1324.26 TOPS/W and an area efficiency of ~230.2 to 4604. SGOPS/mm2 for the CIFAR-10 dataset with the ResNet-20 model. It advances the defined FoM by~2.7X to 3.2X over the prior CIM designs.
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16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips
Jian-Wei Su, Yen-Chi Chou, Ruhui Liu et al. · 2021 · 197 citations
Win-San Khwa, Yen-Cheng Chiu, Chuan-Jia Jhang et al. · 2022 IEEE International Solid- State Circuits Conference (ISSCC) · 2022 · 118 citations