15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips

Xin Si, Yung-Ning Tu, Wei-Hsing Huang, +24

EngineeringMac OperationsHardware AccelerationEdge ComputingHigh-performance Architecture +13

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, +18

EngineeringComputer ArchitectureMulti-channel Memory ArchitectureHigh-performance ArchitectureComputing Systems +16

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips

Jian-Wei Su, Xin Si, Yen-Chi Chou, +20

EngineeringEdge DeviceComputer ArchitectureTwt Multiply CellSram Compute-in-memory Macro +19

15.2 A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating

Jinshan Yue, Xiaoyu Feng, Yifan He, +14

Simultaneous ComputationEngineeringComputer ArchitecturePrevious Cim ChipsHigh-performance Architecture +17

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips

Xin Si, Yung-Ning Tu, Wei-Hsing Huang, +18

IEEE Journal of Solid-State Circuits

EngineeringVlsi DesignProcess VariationEnergy EfficiencyEdge Device +16

A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices

Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, +17

2022 IEEE International Solid- State Circuits Conference (ISSCC)

EngineeringEmerging Memory TechnologyComputer ArchitectureEmbedded Systems8B-mac Operations +19

A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors

Yen-Cheng Chiu, Zhixiao Zhang, Jiajing Chen, +15

IEEE Journal of Solid-State Circuits

Electrical EngineeringMemory ArchitectureEngineeringVlsi DesignHardware Acceleration +11

A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices

Ping-Chun Wu, Jian-Wei Su, Li-Yang Hong, +14

Edge DevicesEngineeringHardware AccelerationEdge ComputingHigh-performance Architecture +12

RRAM-based Spiking Nonvolatile Computing-In-Memory Processing Engine with Precision-Configurable In Situ Nonlinear Activation

Bonan Yan, Qing Yang, Wei-Hao Chen, +11

NeurochipSitu Nonlinear ActivationEngineeringHardware AccelerationHybrid Cmos-rram Integration +11

A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme

Wei-Hao Chen, Wen-Jang Lin, Li-Ya Lai, +8

Non-volatile MemoryElectrical EngineeringMemory ArchitectureEngineeringReram Resistance +13