15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips

Abstract

Advanced AI edge chips require multibit input (IN), weight (W), and output (OUT) for CNN multiply-and-accumulate (MAC) operations to achieve an inference accuracy that is sufficient for practical applications. Computing-in-memory (CIM) is an attractive approach to improve the energy efficiency <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{EF}_{\mathrm{MAC}}]$</tex> of MAC operations under a memory-wall constraint. Previous SRAM-CIM macros demonstrated a binary MAC [4], an in-array 8b W-merging with near-memory computing (NMC) using 6T SRAM cells (limited output precision) [5], a 7b1N-1 bW MAC using a 10T SRAM cell (large area) [3], an 4b1N-5bW MAC with a T8T SRAM cell [1], and 8b1N-1bW NMC with 8T SRAM (long MAC latency <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(T_{\mathrm{AC}})$</tex> ) [2]. However, previous works have not achieved high IN/W/OUT precision with fast <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{T}_{\mathrm{AC}}$</tex> compact-area, high <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{EF}_{\mathrm{MAC}}$</tex> , and robust readout against process variation, due to (1) small sensing margin in word-wise multiple-bit MAC operations, (2) a tradeoff between read accuracy vs. area overhead under process variation, (3) limited <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{EF}_{\mathrm{MAC}}$</tex> due to decoupling of software and hardware development.