Win-San Khwa - Concepedia

Author

Win-San Khwa

Taiwan Semiconductor Manufacturing Company (Taiwan)ORCID

Also Known As

Khwa, Win-San, W. Khwa, W. S. Khwa, W.S. Khwa, Win-San Khwa

Publications

3.2K

Citations

H-Index

Concepts

All Affiliations

Taiwan Semiconductor Manufacturing Company (Taiwan)National Tsing Hua University Georgia Institute of Technology Taiwan Semiconductor Manufacturing Company (United States)National Chung Hsing University

About

Win-San Khwa is an author at Taiwan Semiconductor Manufacturing Company (Taiwan) specializing in computer engineering, engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	31	38	2.9K
2	Computer Engineering	31	38	2.9K
3	Social Sciences	3	3	213
4	Applied Physics	3	3	220
5	Cognitive Science	1	1	65

Win-San Khwa

Publications

3.1K

Citations

H-Index

Page 1

	Year	Citations
15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications Qing Dong, Mahmut E. Sinangil, Burak Erbagci, Machine-learning ApplicationsEngineeringVlsi DesignWeight PrecisionEmerging Memory Technology	2020	310
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors Win-San Khwa, Jiajing Chen, Jiafang Li, EngineeringComputer ArchitectureMulti-channel Memory ArchitectureHigh-performance ArchitectureSparse Neural Network	2018	240
16.1 A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices Cheng-Xin Xue, Je-Min Hung, Hui-Yao Kao, EngineeringEnergy EfficiencyEmerging Memory TechnologyComputer ArchitectureHardware Systems	2021	174
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS Mahmut E. Sinangil, Burak Erbagci, Rawan Naous, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignComputer ArchitectureEmbedded SystemsHardware Systems	2020	158
A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors Xin Si, Meng‐Fan Chang, Win-San Khwa, IEEE Transactions on Circuits and Systems I Regular Papers Artificial IntelligenceEngineeringAdvanced ComputingNeural NetworkComputer Architecture	2019	147
An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices Je-Min Hung, Yen-Hsiang Huang, Sheng-Po Huang, 2022 IEEE International Solid- State Circuits Conference (ISSCC) Non-volatile MemoryEngineeringComputer ArchitectureHardware SystemsSignal Margin	2022	112
A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices Win-San Khwa, Yen-Cheng Chiu, Chuan-Jia Jhang, 2022 IEEE International Solid- State Circuits Conference (ISSCC) EngineeringComputer ArchitectureTiny-al Edge DevicesHigh-performance ArchitectureComputing Systems	2022	112
A four-megabit compute-in-memory macro with eight-bit precision based on CMOS and resistive random-access memory for AI edge devices Je-Min Hung, Cheng-Xin Xue, Hui-Yao Kao, Nature Electronics Hardware SecurityFour-megabit Compute-in-memory MacroEngineeringHardware AccelerationEight-bit Precision	2021	107
A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS Ruiqi Guo, Yonggang Liu, Shixuan Zheng, EngineeringMachine LearningNeural Networks (Machine Learning)Computer ArchitectureNeurochip	2019	97
A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations Yen-Cheng Chiu, Chia-Sheng Yang, Shih-Hsin Teng, 2022 IEEE International Solid- State Circuits Conference (ISSCC) 25.1-55.1Tops/w 8BNon-volatile MemoryEngineeringNeural NetworkComputer Architecture	2022	86

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