Power-efficient Memory Design
Power-Efficient Memory Design is a memory subsystem optimization approach that belongs to the class of memory design methodologies and is distinguished by its primary objective of minimizing energy consumption during data storage and retrieval operations through architectural, circuit-level, and operational techniques.
707
Publications
32.2K
Citations
2.9K
Authors
451
Institutions
Publications per year
2017–2026
193
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707
R. M. Banakar, Stefan Steinke, Bo-Sik Lee et al. · 2002 · 661 citations
Mohammad Nauman, Sohail Khan, Xinwen Zhang · 2010 · 532 citations
Rajeev Balasubramonian, Andrew B. Kahng, Naveen Muralimanohar et al. · ACM Transactions on Architecture and Code Optimization · 2017 · 519 citations
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Pennsylvania State University
State College, United States
17 h-index
67 publications
3.4K citations
IMEC
Leuven, Belgium
17 h-index
103 publications
4.1K citations
Hitachi (Japan)
Tokyo, Japan
17 h-index
70 publications
2.3K citations
Samsung (South Korea)
Seoul, South Korea
15 h-index
292 publications
19.4K citations
Intel (United States)
Santa Clara, United States
14 h-index
46 publications
2.1K citations
National Tsing Hua University
Hsinchu, Taiwan
14 h-index
83 publications
3.9K citations
Korea Advanced Institute of Science and Technology
Daejeon, South Korea
14 h-index
65 publications
2.3K citations
University of Pittsburgh
Pittsburgh, United States
13 h-index
43 publications
3.1K citations
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71 publications · 4K citations
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30 publications · 931 citations
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17 publications · 455 citations
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14 publications · 520 citations
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10 publications · 533 citations
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