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Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
768
Citations
18
References
2009
Year
Unknown Venue
Hardware SecurityNon-volatile MemoryElectrical EngineeringEngineeringEmerging Memory TechnologyPcm CellsComputer EngineeringComputer ArchitectureStart-gap Wear LevelingPcm-based Main MemoryComputer ScienceSemiconductor MemoryPcm SystemParallel ComputingMicroelectronicsPhase Change MemoryPhase-change MemoryMemory Architecture
Phase‑Change Memory (PCM) is an emerging, cost‑effective, power‑efficient main‑memory technology, but its cells can endure only 10^7–10^8 writes, limiting system lifetime to only a few years. The study aims to use wear‑leveling to make PCM writes uniform. Existing wear‑leveling methods rely on large storage tables and indirection, incurring significant area and latency overheads. The authors demonstrate that write non‑uniformity shortens PCM lifetime by up to 20×.
Phase Change Memory (PCM) is an emerging memory technology that can increase main memory capacity in a cost-effective and power-efficient manner. However, PCM cells can endure only a maximum of 107 - 108 writes, making a PCM based system have a lifetime of only a few years under ideal conditions. Furthermore, we show that non-uniformity in writes to different cells reduces the achievable lifetime of PCM system by 20x. Writes to PCM cells can be made uniform with Wear-Leveling. Unfortunately, existing wear-leveling techniques require large storage tables and indirection, resulting in significant area and latency overheads.
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