Cryogenic Characterization and Model Extraction of 5nm Technology Node FinFETs

Abstract

We present cryogenic characterization and compact model extraction of commercially fabricated 5nm technology FinFETs. A modified industry-standard BSIM-CMG model is used to accurately model band-tail, mobility, and velocity saturation effects up to 10K. At 10K, n-FinFET and p-FinFET show 87mV and 92mV threshold voltage shift and sub-threshold slopes of 12.7 and 16.7mV/decade (83% and 78% improvement), respectively. The simulated inverter and ring oscillator at 10K in iso I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> condition show 38% and 36.53% delay improvement for V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> = 0.75V, respectively. At V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> = 0.35V, inverter simulations show ∽ 70% improvement in delay and Power-Delay-Product. Static leakage and power dissipation are major challenges in FinFETs; the above-mentioned performance enhancements highlight the potential of characterized technology in quantum computers.