2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2003 · 87 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSystem-on-chip DesignCmos Circuit DesignDesign For TestabilityIntegrated Circuit DesignLeakage Power ReductionPhysical DesignAdaptive Body Bias ControlBody BiasingLeakageLeakage PowerOn-chip Variation AnalysisProcess Variation Aware Leakage ReductionProcess Variation CompensationReverse Body Biasing
Measurements on a 150 nm CMOS test chip show that on-chip bidirectional adaptive body biasing compensates effectively for die-to-die parameter variation to meet both frequency and leakage requirements. An enhancement of this technique to correct for within-die variations triples the accepted die count in the highest frequency bin.
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