Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution

Abstract

A processor maximum clock frequency (FMAX) distribution is significantly influenced by the magnitude of critical path delay deviations resulting from both die-to-die (inter-die) and within-die (intra-die) fluctuations. FMAX is a measurement performed at wafer sort in which each functional die is tested for its maximum operating clock frequency. Die-to-die fluctuations resulting from lot-to-lot, wafer-to-wafer and some sources of the within-wafer variations affect every element on a chip equally. Conversely, within-die fluctuations consisting of both random and systematic components produce a nonuniformity of electrical characteristics across the chip. The FMAX distribution model is based upon statistical simulations of critical paths for a 0.25/spl mu/m Pentium-family processor.