Clock Jitter Modeling
Clock Jitter Modeling is a timing modeling technique that characterizes the deviation in the timing of clock signal transitions from their ideal positions to quantify the impact of temporal instability on synchronous digital circuit performance.
134
Publications
6K
Citations
357
Authors
149
Institutions
Publications per year
2017–2026
10
Parents
134
1–5 of 134
357
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149
Intel (United States)
Santa Clara, United States
10 h-index
30 publications
2.8K citations

University of Massachusetts Amherst
Amherst Center, United States
5 h-index
15 publications
221 citations
Rambus (United States)
Sunnyvale, United States
4 h-index
15 publications
428 citations

National Taiwan University
Taipei, Taiwan
4 h-index
8 publications
346 citations

Cornell University
Ithaca, United States
3 h-index
4 publications
119 citations

University of Twente
Enschede, The Netherlands
3 h-index
9 publications
246 citations
Analog Devices (United States)
Norwood, United States
3 h-index
9 publications
165 citations
University of California, Los Angeles
Los Angeles, United States
3 h-index
6 publications
554 citations
1–8 of 149
12 publications · 257 citations
11
h-index
10 publications · 1.6K citations
10
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6 publications · 171 citations
6
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5 publications · 129 citations
5
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5 publications · 211 citations
5
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1–5