Clock Jitter Modeling

Clock Jitter Modeling is a timing modeling technique that characterizes the deviation in the timing of clock signal transitions from their ideal positions to quantify the impact of temporal instability on synchronous digital circuit performance.

134

Publications

6K

Citations

357

Authors

149

Institutions

Publications per year

2017–2026

10

Authors

357

  1. DO
    Dan Oh

    Rambus (United States), United States

    4 publications · 66 citations

    4

    h-index

  2. WB
    Wayne Burleson

    University of Massachusetts Amherst, United States

    3 publications · 41 citations

    3

    h-index

  3. EA
    Eric A.M. Klumperink

    University of Twente, Netherlands

    3 publications · 82 citations

    3

    h-index

  4. OF
    Orla Feely

    University College Dublin, Ireland

    3 publications · 62 citations

    3

    h-index

  5. JL
    Jri Lee

    National Taiwan University, Taiwan

    3 publications · 276 citations

    3

    h-index

1–5 of 357

Venues

  1. 11

    h-index

  2. IEEE Journal of Solid-State Circuits

    10 publications · 1.6K citations

    10

    h-index

  3. 6

    h-index

  4. 5

    h-index

  5. 5

    h-index

1–5