Jitter analysis of high-speed sampling systems

Abstract

The jitter of such practical sampling systems as analog-to-digital converters, sample-and-hold circuits, and samplers is discussed. A model for estimating jitter is proposed. In this model, total jitter is composed of sampling circuit jitter, analog input signal jitter, and sampling clock jitter. Using this model, jitter is broken up into three components. To evaluate the model, a precise method for measuring jitter is devised. This method, based on sampling sine-wave signal-to-noise ratio calculations, enables separation of jitter and amplitude noise. The performance limit of converters as evaluated by the model is discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>