Reliability performance of ETOX based flash memories

Abstract

The reliability performance of a 64 K flash memory based on a single-transistor, floating-gate memory cell is considered. The reliability performance of these memories, before program/erase cycling, matches that of UV EPROMs. Cycling generally does not introduce defect-related failures common to some EEPROMs. However, it may aggravate two intrinsic instabilities found in the UV EPROM (intrinsic charge loss and the DC program disturb mechanism). Experience shows that these are related effects caused by injection of holes during the erase step of the cycle. High source-to-substrate electric fields, during erase, generate these holes. Channel hot electron injection, for programming, plays no significant role in the observed degradation. These cycling effects can be addressed through incorporation of additional margin into the flash cell. Through such cell optimization, the reliability of these memories is made equivalent to that of conventional UV EPROMs, even after hundreds of program/erase cycles.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>