Compact Modeling of Multidomain Ferroelectric FETs: Charge Trapping, Channel Percolation, and Nucleation-Growth Domain Dynamics

Abstract

The (doped-)hafnia-based' ferroelectric FET (FeFET) is a promising candidate for low-power nonvolatile memories and shows potential use as a steep-slope low-power logic device. This requires accurate modeling of the metal-ferroelectric-insulator-silicon (MFIS) gate stack electrostatics. Here, we present a hardware-validated FeFET compact model that resolves three key aspects in the MFIS electrostatics pertaining to a multidomain ferroelectric (FE) layer: 1) the nonradiative multiphonon process-based charge trapping; 2) the source-to-drain channel percolation due to spatial nonuniformity of FE domain switching; and 3) the nucleation-growth domain reversal dynamics using a phenomenological formalism. The polarization charge is calculated by discretized domain switching in transient under distributed coercive fields. Based on the comparison of the model versus experimental data on Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> n-FeFET hardware, we prove that the onset of FE V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> lowering starts with the source-to-drain percolation path formation when enough FE domains have been flipped up by the gate bias. We further demonstrate that the field-independent domain growth is the fundamental origin of the measured steep subthreshold slope during the downward I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> - V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> sweep. The model ultimately aims to lay down the groundwork for a unified FeFET compact model for both memory- and logic-oriented applications.