A Device Design for 5 nm Logic FinFET Technology

Abstract

In this paper, we proposed a 5 nm FINFET device, which is based on typical 5 nm logic design rules. We have performed an optimization on the process parameters and iterate through device simulation with the consideration of current process capability. Based on our preferred device architecture, we provide our process key dimensions, and simulated device DC/AC performance, and some parasitic parameters. As a part of the final evaluation, Ring Oscillator (RO) simulation result has been checked, which demonstrates that the Performance Per Area (PPA) is close to industry reference 5 nm performance.