Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs

Abstract

State-of-the-art in-memory computing (IMC) architectures employ an array of homogeneous tiles and severely underutilize processing elements (PEs). In this article, the authors propose an area and energy optimization methodology to generate a heterogeneous IMC architecture coupled with an optimized Network-on-Chip (NoC) for deep neural network (DNN) acceleration. -Yiran Chen, Duke University.